- 鍾思齊
Publications
 
Papers
  • Szu-Chi Chung, Shih-Hao Huang, Po-Yao Niu, Su-Yun Huang, Wei-Hau Chang, I-Ping Tu, 2019, Two-Stage Dimension Reduction Method For Cryo-EM Image Processing, In preparation. (IF 0).
  • Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee, 2017, An Improved DPA Countermeasure Based on UDRPG for IoT Applications, IEEE Transactions on Circuits and Systems I (TCAS-I) (IF 0).
  • Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen- Yi Lee, 2015, Efficient Hardware Architecture of $\eta_T$ Pairing Accelerator Over Characteristic Three, IEEE Transactions on Very Large Scale Integration (VLSI) System (IF 0).
  • Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee, 2014, Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) System (IF 0).
Conference Papers
  • Sung-Shine Lee, Szu-Chi Chung, Chun-Yuan Yu, Hsie-Chia Chang, Chen-Yi Lee, 2015, A New Power Analysis Attack on Stream cipher Trivium-64, VLSI Design/CAD Symposium (VLSI-CAD) (IF 0).
  • Szu-Chi Chung, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee, 2014, Implementing Bilinear Pairing Accelerator Using Residue Number System, VLSI Design/CAD Symposium (VLSI-CAD) (IF 0).
  • Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee, 2013, A $3.40ms/GF(p_{521})$ and $2.77ms/GF(2^{521})$ DF-ECC Processor with Side-Channel Attack Resistance, International Solid-State Circuits Conference (ISSCC) (IF 0).
  • Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee, 2012, An Efficient Countermea- sure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor, Conference on Cryptographic Hardware and Embedded Systems (CHES) (IF 0).
  • Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee, 2012, High-performance elliptic curve cryptographic processor over $GF(p)$ with SPA resistance, IEEE International Symposium on Circuits and Systems (ISCAS) (IF 0).